The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2025
Filed:
Aug. 03, 2021
Applicant:
Flex Ltd., Singapore, SG;
Inventors:
Cheng Yang, Shanghai, CN;
Dongkai Shangguan, San Jose, CA (US);
Assignee:
Flex Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/94 (2013.01); H01L 2224/0613 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01);
Abstract
A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.