The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Sep. 10, 2021
Applicant:
Arteris, Inc., Campbell, CA (US);
Inventors:
Moez Cherif, San Jose, CA (US);
Benoit De Lescure, Campbell, CA (US);
Xavier Van Ruymbeke, Montigny-le-Bretonneux, FR;
Assignee:
ARTERIS, INC., Campbell, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 41/14 (2022.01); G06F 30/32 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H04L 41/0803 (2022.01); H04L 41/12 (2022.01); H04L 43/0811 (2022.01); H04L 45/00 (2022.01); H04L 67/1001 (2022.01); H04L 69/329 (2022.01); H04W 40/32 (2009.01); H04W 84/18 (2009.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
H04L 41/145 (2013.01); G06F 30/32 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H04L 41/0803 (2013.01); H04L 41/12 (2013.01); H04L 43/0811 (2013.01); H04L 45/46 (2013.01); H04L 67/1001 (2022.05); H04L 69/329 (2013.01); H04W 40/32 (2013.01); H04W 84/18 (2013.01); G06F 2115/02 (2020.01);
Abstract
Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.