The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Feb. 09, 2022
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Yu-Lien Huang, Jhubei, TW;
Tze-Liang Lee, Hsinchu, TW;
Jr-Hung Li, Chupei, TW;
Chi-Hao Chang, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66795 (2013.01); H01L 29/78696 (2013.01);
Abstract
A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.