The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
May. 07, 2021
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chih-Ching Wang, Kinmen County, TW;
Wen-Yuan Chen, Taoyuan County, TW;
Wen-Hsing Hsieh, Hsinchu, TW;
Kuan-Lun Cheng, Hsin-Chu, TW;
Chung-Wei Wu, Hsin-Chu County, TW;
Zhiqiang Wu, Hsinchu County, TW;
TAIWAN SEMICONDCUTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.