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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12237399 B1

PDFFull Text
Date of Patent:
Feb. 25, 2025

Filed:

Aug. 27, 2021

Nano-fet transistor with alternating nanostructures and method of forming thereof

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Te-En Cheng, Taoyuan, TW;

Yung-Cheng Lu, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Wei-Yang Lee, Taipei, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

William B Partridge

Assistant Examiner:

David Paul Sedorook

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

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