The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Dec. 29, 2021
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Jiun-Yun Li, Hsinchu, TW;

Pao-chuan Shih, Hsinchu, TW;

Wei-Chih Hou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/73 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 29/2003 (2013.01); H01L 29/42364 (2013.01); H01L 29/66446 (2013.01); H01L 29/7311 (2013.01); H01L 29/7827 (2013.01); H01L 29/7831 (2013.01);
Abstract

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.


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