The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Apr. 05, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Daniel Chanemougame, Niskayuna, NY (US);

Lars Liebmann, Halfmoon, NY (US);

Jeffrey Smith, Clifton Park, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 23/5286 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.


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