The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Nov. 02, 2022
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Minjian Wu, Shanghai, CN;
Hui Wang, Shanghai, CN;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/00 (2019.01); G06F 3/00 (2006.01); G06F 3/06 (2006.01); G06F 16/16 (2019.01); G06F 16/17 (2019.01); G06F 16/172 (2019.01); G06F 16/174 (2019.01);
U.S. Cl.
CPC ...
G06F 16/1724 (2019.01); G06F 3/0608 (2013.01); G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0649 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 16/164 (2019.01); G06F 16/172 (2019.01); G06F 16/1727 (2019.01); G06F 16/174 (2019.01);
Abstract
Apparatuses, systems, and methods for using defrag levels to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include setting a first defrag level for a memory device, determining if a buffer is full while performing defrag operations on the memory device according to the first defrag level, setting a second defrag level for the memory device in response to determining the buffer is full while performing defrag operations according to the first defrag level.