The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Dec. 26, 2020
Intel Corporation, Santa Clara, CA (US);
Rajat Agarwal, Portland, OR (US);
Hsing-Min Chen, Santa Clara, CA (US);
Wei P. Chen, Portland, OR (US);
Wei Wu, Portland, OR (US);
Jing Ling, Milpitas, CA (US);
Kuljit S. Bains, Olympia, WA (US);
Kjersten E. Criss, Portland, OR (US);
Deep K. Buch, Folsom, CA (US);
Theodros Yigzaw, Sherwood, OR (US);
John G. Holm, Beaverton, OR (US);
Andrew M. Rudoff, Boulder, CO (US);
Vaibhav Singh, Hillsboro, OR (US);
Sreenivas Mandava, Los Altos, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.