The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2025
Filed:
Aug. 03, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Inventors:
Jen-Yuan Chang, Hsinchu, TW;
Chia-Ping Lai, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/06 (2013.01); H01L 24/29 (2013.01); H01L 24/30 (2013.01); H01L 25/0657 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/30181 (2013.01); H01L 2225/06541 (2013.01);
Abstract
A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.