The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2025
Filed:
Mar. 31, 2022
Intel Ndtm Us Llc, Santa Clara, CA (US);
Aliasgar S. Madraswala, Folsom, CA (US);
Ali Khakifirooz, Brookline, MA (US);
Bhaskar Venkataramaiah, Folsom, CA (US);
Sagar Upadhyay, Folsom, CA (US);
Yogesh B. Wakchaure, Folsom, CA (US);
Intel NDTM US LLC, Santa Clara, CA (US);
Abstract
Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.