The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Sep. 09, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Edmund Gieske, Boise, ID (US);

Cagdas Dirik, Boise, ID (US);

Robert M. Walker, Boise, ID (US);

Sujeet Ayyapureddi, Boise, ID (US);

Niccolo Izzo, Boise, ID (US);

Markus Geiger, Boise, ID (US);

Yang Lu, Boise, ID (US);

Ameen Akel, Boise, ID (US);

Elliott C. Cooper-Balis, Boise, ID (US);

Danilo Caraccio, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/406 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40618 (2013.01); G11C 11/40611 (2013.01); G11C 29/52 (2013.01);
Abstract

An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.


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