The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Aug. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Yu Chang, New Taipei, TW;

Meng-Han Lin, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Bo-Feng Young, Taipei, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); G11C 11/22 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); G11C 11/2255 (2013.01); H01L 23/535 (2013.01); H01L 29/66787 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/10 (2023.02); H10B 51/30 (2023.02);
Abstract

A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.


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