The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Jan. 19, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yun-Wei Cheng, Hsinchu, TW;

Chun-Wei Chia, Hsinchu, TW;

Chun-Hao Chou, Hsinchu, TW;

Kuo-Cheng Lee, Hsinchu, TW;

Ying-Hao Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 23/562 (2013.01); H01L 27/14621 (2013.01); H01L 27/1463 (2013.01); H01L 27/14636 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01);
Abstract

A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.


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