The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Sep. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Krishna Bharath, Phoenix, AZ (US);

William J. Lambert, Tempe, AZ (US);

Haifa Hariri, Phoenix, AZ (US);

Siddharth Kulasekaran, Chandler, AZ (US);

Mathew Manusharow, Phoenix, AZ (US);

Anne Augustine, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/64 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01);
U.S. Cl.
CPC ...
H01L 23/645 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/3025 (2013.01);
Abstract

Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.


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