The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

May. 18, 2022
Applicant:

SK Keyfoundry Inc., Cheongju-si, KR;

Inventors:

Hee Hwan Ji, Daejeon, KR;

Ji Man Kim, Cheongju-si, KR;

Song Hwa Hong, Cheongju-si, KR;

Bo Seok Oh, Cheongju-si, KR;

Assignee:

SK keyfoundry Inc., Cheongju-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823443 (2013.01); H01L 21/2652 (2013.01); H01L 21/266 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 29/0886 (2013.01); H01L 29/1045 (2013.01); H01L 29/1095 (2013.01); H01L 29/66598 (2013.01); H01L 29/66659 (2013.01); H01L 29/66689 (2013.01); H01L 29/7835 (2013.01); H01L 29/7836 (2013.01); H01L 21/823462 (2013.01); H01L 27/088 (2013.01); H01L 29/41775 (2013.01); H01L 29/42368 (2013.01); H01L 29/665 (2013.01);
Abstract

The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.


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