The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Nov. 17, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Mark I. Gardner, Albany, NY (US);

H. Jim Fulford, Albany, NY (US);

Partha Mukhopadhyay, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 27/092 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01);
Abstract

Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers include a first layer stack of a first transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material. The stack of layers can include a second layer stack of a second transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material, the second layer stack associated with a second transistor structure. The first and second transistor structures are separated by one or more dielectric materials. The method can include forming a channel opening in the stack. The method includes selectively forming a first channel structure within the channel opening and selectively forming a second channel structure within the channel opening.


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