The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Jun. 14, 2021
Applicants:

Soitec, Bernin, FR;

National University of Singapore, Singapore, SG;

Inventors:

Bich-Yen Nguyen, Austin, TX (US);

Christophe Maleville, Lumbin, FR;

Walter Schwarzenbach, Saint Nazaire Les Eymes, FR;

Gong Xiao, Singapore, SG;

Aaron Thean, Singapore, SG;

Chen Sun, Singapore, SG;

Haiwen Xu, Singapore, SG;

Assignees:

National University of Singapore, Singapore, SG;

Soitec, Bernin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/84 (2006.01); H01L 27/10 (2006.01); H01L 27/12 (2006.01); H01L 29/161 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1037 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/02667 (2013.01); H01L 21/26526 (2013.01); H01L 21/845 (2013.01); H01L 27/10 (2013.01); H01L 27/1211 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/7838 (2013.01);
Abstract

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.


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