The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Jun. 07, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Guo-Huei Wu, Tainan, TW;

Po-Chun Wang, Hsinchu, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Chih-Liang Chen, Hsinchu, TW;

Li-Chun Tien, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 23/538 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 23/5384 (2013.01); H01L 29/0649 (2013.01);
Abstract

A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.


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