The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Mar. 17, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Owen R. Fay, Meridian, ID (US);

Chan H. Yoo, Boise, ID (US);

Mark E. Tuttle, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/561 (2013.01); H01L 23/3171 (2013.01); H01L 23/53238 (2013.01); H01L 24/17 (2013.01); H01L 24/96 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/165 (2013.01);
Abstract

Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.


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