The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Dec. 27, 2021
Applicant:

Yibu Semiconductor Co., Ltd., Shanghai, CN;

Inventor:

Weiping Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/49822 (2013.01); H01L 24/13 (2013.01); H01L 24/96 (2013.01); H01L 2224/11003 (2013.01); H01L 2224/11005 (2013.01); H01L 2224/13023 (2013.01);
Abstract

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.


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