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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12217053 B1

PDFFull Text
Date of Patent:
Feb. 04, 2025

Filed:

Dec. 04, 2023

Instructions and logic to perform floating point and integer operations for machine learning

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Himanshu Kaul, Portland, OR (US);

Mark A. Anders, Hillsboro, OR (US);

Sanu K. Mathew, Hillsboro, OR (US);

Anbang Yao, Beijing, CN;

Joydeep Ray, Folsom, CA (US);

Ping T. Tang, Edison, NJ (US);

Michael S. Strickland, Sunnyvale, CA (US);

Xiaoming Chen, Shanghai, CN;

Tatiana Shpeisman, Menlo Park, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Kamal Sinha, Rancho Cordova, CA (US);

Balaji Vembu, Folsom, CA (US);

Nicolas C. Galoppo Von Borries, Portland, OR (US);

Eriko Nurvitadhi, Hillsboro, OR (US);

Rajkishore Barik, Santa Clara, CA (US);

Tsung-Han Lin, Campbell, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Sanjeev Jahagirdar, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Jaffery Watson Mendonsa & Hamilton LLP;

Primary Examiner:

Corey S Faherty

Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06F 9/38 (2018.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G09G 5/393 (2006.01); G06F 1/16 (2006.01); G06F 17/16 (2006.01); G06N 20/00 (2019.01); G06T 15/00 (2011.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 7/483 (2013.01); G06F 7/5443 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/3851 (2013.01); G06F 9/3888 (2023.08); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G09G 5/393 (2013.01); G06F 1/16 (2013.01); G06F 9/30025 (2013.01); G06F 9/3013 (2013.01); G06F 17/16 (2013.01); G06F 2207/3824 (2013.01); G06N 20/00 (2019.01); G06T 15/005 (2013.01);
Abstract

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

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