The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

May. 14, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Alexander Derrickson, Saratoga Springs, NY (US);

Anupam Dutta, Bangalore, IN;

John Pekarik, Underhill, VT (US);

Vibhor Jain, Essex Junction, VT (US);

V V S S Satyasuresh Choppalli, Bangalore, IN;

Rui Tze Toh, Singapore, SG;

Oscar Restrepo, Halfmoon, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/737 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/737 (2013.01); H01L 29/0808 (2013.01); H01L 29/0821 (2013.01); H01L 29/1008 (2013.01); H01L 29/165 (2013.01); H01L 29/41708 (2013.01); H01L 29/42304 (2013.01); H01L 29/66242 (2013.01);
Abstract

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.


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