The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Mar. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Su-Jen Sung, Zhubei, TW;

Jr-Hung Li, Chupei, TW;

Tze-Liang Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3185 (2013.01); H01L 21/56 (2013.01); H01L 23/291 (2013.01); H01L 23/3192 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/80 (2013.01); H01L 24/48 (2013.01); H01L 25/105 (2013.01); H01L 2224/08148 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48229 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/1041 (2013.01);
Abstract

A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.


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