The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Oct. 17, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Kaijin Huang, Wuhan, CN;

Jin Lyu, Wuhan, CN;

Gang Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 7/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 7/04 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01);
Abstract

A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The first drain dummy line voltage is greater than the first DSG voltage.


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