Concurrent slow-fast memory cell programming

Abstract

Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.