The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

May. 31, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Giorgio Servalli, Fara Gera d'Adda, IT;

Marcello Mariani, Milan, IT;

Agostino Pirovano, Milan, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 5/06 (2006.01); H01L 29/51 (2006.01); H10B 53/10 (2023.01); H10B 53/20 (2023.01);
U.S. Cl.
CPC ...
G11C 11/2253 (2013.01); G11C 5/063 (2013.01); G11C 11/221 (2013.01); H01L 29/516 (2013.01); H10B 53/10 (2023.02); H10B 53/20 (2023.02);
Abstract

Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.


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