The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

May. 02, 2024
Applicant:

Eliyan Corporation, Santa Clara, CA (US);

Inventor:

Ramin Farjadrad, Los Altos, CA (US);

Assignee:

Eliyan Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 115/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 2115/12 (2020.01);
Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a logic base die for inclusion in a chiplet-based multi-chip module (MCM) is disclosed. The logic base die includes a first port interface for coupling to an interface beachfront of a first integrated circuit (IC) chiplet. The first port interface is to receive data of a first bandwidth via the interface beachfront via a first set of traces formed in a micro-bump advanced-package routing layer. A memory port provides a first portion of the first bandwidth to at least a first memory stack configured for positioning on the logic base die. A second port interface couples to the first port interface and utilizes a second portion of the first bandwidth.


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