Memory chiplet with efficient mapping of memory-centric interface to die-to-die (d2d) unit interface modules

Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes a D2D interface of a first type for coupling to a host IC chip via multiple lanes. The D2D interface includes multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes. A memory port includes a memory physical interface of a first memory type for accessing memory storage of the first memory type. The memory physical interface of the first memory type includes a second set of signal path resources corresponding to multiple memory channels of the first memory type. Mapping circuitry maps the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the first signal path resources for an integer number of the multiple unit interface modules.