The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Nov. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hung-Shu Huang, Taichung, TW;

Ming Chyi Liu, Hsinchu, TW;

Tung-He Chou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03B 13/36 (2021.01); G01S 3/00 (2006.01); G06V 10/40 (2022.01); G06V 10/75 (2022.01); G06V 40/20 (2022.01); H01L 21/00 (2006.01); H01L 21/3213 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H04N 5/262 (2006.01); H04N 23/45 (2023.01); H04N 23/61 (2023.01); H04N 23/63 (2023.01); H04N 23/67 (2023.01); H04N 23/69 (2023.01); H04N 23/698 (2023.01); H04N 23/90 (2023.01);
U.S. Cl.
CPC ...
G03B 13/36 (2013.01); G01S 3/00 (2013.01); G06V 10/40 (2022.01); G06V 10/751 (2022.01); G06V 40/20 (2022.01); H01L 21/00 (2013.01); H01L 21/32139 (2013.01); H01L 21/823456 (2013.01); H01L 29/42372 (2013.01); H01L 29/42376 (2013.01); H01L 29/4238 (2013.01); H01L 29/42384 (2013.01); H01L 29/66613 (2013.01); H01L 29/66621 (2013.01); H01L 29/66628 (2013.01); H01L 29/7834 (2013.01); H01L 29/7835 (2013.01); H01L 29/7836 (2013.01); H04N 5/2628 (2013.01); H04N 23/45 (2023.01); H04N 23/61 (2023.01); H04N 23/63 (2023.01); H04N 23/675 (2023.01); H04N 23/69 (2023.01); H04N 23/698 (2023.01); H04N 23/90 (2023.01);
Abstract

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.


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