The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Jul. 10, 2023
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Janbo Zhang, Quanzhou, CN;

Li-Wei Feng, Quanzhou, CN;

Yu-Cheng Tung, Quanzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H10B 12/36 (2023.02); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/6656 (2013.01); H10B 12/056 (2023.02);
Abstract

The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.


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