The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Aug. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Xuan Huang, Hsinchu, TW;

Hou-Yu Chen, Zhubei, TW;

Ching-Wei Tsai, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Chung-Hui Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/12 (2006.01); G11C 11/22 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/845 (2013.01); H01L 23/5286 (2013.01); H01L 23/5329 (2013.01); H01L 27/1211 (2013.01); G11C 11/221 (2013.01); H01L 21/7681 (2013.01); H01L 21/823821 (2013.01); H01L 23/528 (2013.01); H01L 27/14636 (2013.01); H01L 27/14641 (2013.01);
Abstract

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.


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