The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2025
Filed:
May. 22, 2023
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Chan H. Yoo, Boise, ID (US);
Owen R. Fay, Meridian, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/36 (2006.01); H01L 23/00 (2006.01); H01L 23/42 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H05K 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/36 (2013.01); H01L 23/42 (2013.01); H01L 23/49822 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H05K 7/2039 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H05K 2201/10378 (2013.01);
Abstract
Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermal management layer disposed between the first and second devices. The thermal management layer may be configured to reduce heat transfer between the first and second devices.