The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

May. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsin-Li Cheng, Hsin Chu, TW;

Liang-Tai Kuo, Zhudong Township, TW;

Yu-Chi Chang, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/3115 (2006.01); H01L 21/324 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/513 (2013.01); H01L 21/31155 (2013.01); H01L 21/324 (2013.01); H01L 29/66492 (2013.01); H01L 29/6656 (2013.01);
Abstract

In some embodiments, a semiconductor device is provided. The semiconductor device includes a gate electrode disposed on a substrate. Source/drain regions are disposed on or within the substrate along opposing sides of the gate electrode. A noise reducing component is arranged along an upper surface of the gate electrode and/or along an upper surface of the substrate over the source/drain regions. A cap layer covers the upper surface of the gate electrode and/or the upper surface of the substrate over the source/drain regions. An inter-level dielectric (ILD) is disposed over and along one or more sidewalls of the cap layer.


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