The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Jun. 01, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Wan-Yu Lo, Zhongli, TW;

Chung-Hsing Wang, Baoshan Township, TW;

Chin-Shen Lin, Taipei, TW;

Kuo-Nan Yang, Hsinchu, TW;

Hsiang-Ku Shen, Hsinchu, TW;

Dian-Hau Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 28/40 (2013.01);
Abstract

A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.


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