The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2025
Filed:
Jun. 25, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jorge Parra, El Dorado Hills, CA (US);
Supratim Pal, Folsom, CA (US);
Jiasheng Chen, El Dorado Hills, CA (US);
Chandra Gurram, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01); G06F 1/329 (2019.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5027 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 9/5094 (2013.01); G06F 15/8046 (2013.01); G06T 1/20 (2013.01);
Abstract
A processing apparatus can include a general-purpose parallel processing engine comprising a matrix accelerator including a multi-stage systolic array, where each stage includes multiple processing elements associated with multiple processing channels. The multiple processing elements are configured to receive output sparsity metadata that is independent of input sparsity of input matrix elements and perform processing operations on the input matrix elements based on the output sparsity metadata.