The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Aug. 23, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Gulbagh Singh, Uttar Pradesh, IN;

Cheng-Yeh Huang, Tainan, TW;

Chin-Nan Chang, Tainan, TW;

Chih-Ming Lee, Tainan, TW;

Chi-Yen Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/76202 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 29/456 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor strip structure over a semiconductor substrate. The semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, and the spacing region is an undoped region. The method includes performing an implantation process over the first doped region and the spacing region to convert a first upper portion of the first doped region and a second upper portion of the spacing region into a continuous disorder region. The method includes forming a metal-semiconductor compound layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region after the implantation process.


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