The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Jul. 18, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc China Company, Limited, Shanghai, CN;
Tsmc Nanjing Company, Limited, Nanjing, CN;
XiuLi Yang, Hsinchu, TW;
Ching-Wei Wu, Hsinchu, TW;
He-Zhou Wan, Hsinchu, TW;
Kuan Cheng, Hsinchu, TW;
Luping Kong, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC CHINA COMPANY, LIMITED, Shanghai, CN;
TSMC NANJING COMPANY, LIMITED, Nanjing, CN;
Abstract
A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.