The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Oct. 07, 2022
Intel Corporation, Santa Clara, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Aravindh Anantaraman, Folsom, CA (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Valentin Andrei, San Jose, CA (US);
Nicolas Galoppo Von Borries, Portland, OR (US);
Varghese George, Folsom, CA (US);
Mike Macpherson, Portland, OR (US);
Subramaniam Maiyuran, Gold River, CA (US);
Joydeep Ray, Folsom, CA (US);
Lakshminarayanan Striramassarma, Folsom, CA (US);
Scott Janus, Loomis, CA (US);
Brent Insko, Portland, OR (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Kamal Sinha, Rancho Cordova, CA (US);
Arthur Hunter, Cameron Park, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
David Puffer, Tempe, AZ (US);
James Valerio, North Plains, OR (US);
Ankur N. Shah, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.