The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Dec. 06, 2021
Applicant:

Hangzhou Silicon-magic Semiconductor Technology Co., Ltd., Hangzhou, CN;

Inventors:

Bing Wu, Hangzhou, CN;

Jiakun Wang, Hangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/765 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/765 (2013.01); H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01); H01L 29/7827 (2013.01);
Abstract

Disclosed is a trench-type MOSFET and a method for manufacturing the same. The method comprises: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding conductor in the trench; forming an opening on two sides of the shielding conductor in the trench, wherein the opening is separated from the shielding conductor by the first insulating layer; forming a gate dielectric layer and a gate conductor in the opening, wherein the trench extends from an upper surface of the semiconductor substrate into the semiconductor substrate, the first insulating layer covers a sidewall and a bottom of the trench and separates the shielding conductor from the semiconductor substrate, the gate dielectric layer at least covers a sidewall of the opening. The method simplifies the process steps of forming the trench-type MOSFET compared with the prior art, and reduces process errors.


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