The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Oct. 26, 2022
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Ryan Sporer, Mechanicville, NY (US);

George R. Mulfinger, Wilton, NY (US);

Yusheng Bian, Ballston Lake, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 27/146 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 27/14612 (2013.01); H01L 27/14643 (2013.01); H01L 29/0649 (2013.01);
Abstract

Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.


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