The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Oct. 28, 2021
Applicant:

Stmicroelectronics Pte Ltd, Singapore, SG;

Inventor:

Jing-En Luan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01S 5/02218 (2021.01); H01S 5/02315 (2021.01); H01S 5/02345 (2021.01);
U.S. Cl.
CPC ...
H01L 21/4803 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01S 5/02218 (2021.01); H01S 5/02315 (2021.01); H01S 5/02345 (2021.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01);
Abstract

A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.


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