The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Aug. 10, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi-Chun Shih, Taipei, TW;

Chia-Fu Lee, Hsinchu, TW;

Yu-Der Chih, Hsinchu, TW;

Jonathan Tsung-Yung Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 5/06 (2013.01); G11C 7/1045 (2013.01); G11C 7/1048 (2013.01); G11C 16/0433 (2013.01); G11C 16/30 (2013.01);
Abstract

Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.


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