The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Mar. 09, 2021
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Zhongkui Tan, Fremont, CA (US);

Qian Fu, Pleasanton, CA (US);

Ying Wu, Livermore, CA (US);

Qing Xu, Fremont, CA (US);

John Drewery, San Jose, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/32 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01); H01J 37/32082 (2013.01); H01J 37/32146 (2013.01); H01J 37/32165 (2013.01); H01J 37/32174 (2013.01); H01J 37/3244 (2013.01); H01J 37/32715 (2013.01); H01L 21/30655 (2013.01); H01L 21/308 (2013.01); H01L 21/31116 (2013.01); H01L 21/31122 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/67069 (2013.01); H01J 2237/334 (2013.01); Y02P 80/30 (2015.11);
Abstract

A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.


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