The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2024
Filed:
Aug. 10, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 11/4074 (2006.01); G11C 11/4096 (2006.01); G11C 11/4099 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 8/10 (2013.01); G11C 11/4074 (2013.01); G11C 11/4096 (2013.01); G11C 11/4099 (2013.01); G11C 17/16 (2013.01);
Abstract
A memory circuit includes a bank of non-volatile memory (NVM) devices, a high-voltage (HV) driver, a global HV power switch configured to generate a HV power signal, and a HV power switch coupled between the global HV switch and the HV driver. The HV power switch is configured to, responsive to the HV power signal, output power and ground signals, each of the power signal and the ground signal having first and second voltage levels, and the HV driver is configured to output a HV activation signal to a column of the bank of NVM devices responsive to the power signal and the ground signal.