The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2024
Filed:
Oct. 19, 2021
Changxin Memory Technologies, Inc., Hefei, CN;
Chuanjiang Chen, Hefei, CN;
Kang Zhao, Hefei, CN;
Li Bai, Hefei, CN;
Li Tang, Hefei, CN;
Jing Xu, Hefei, CN;
CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei, CN;
Abstract
A layout method for an integrated circuit includes the following steps: providing a layout, the layout including a first element region and a second element region, a spacing region being provided between the first element region and the second element region; and detecting whether a width of the spacing region is less than a preset width, and if yes, marking at least one of the first element region, the second element region and the spacing region, the preset width being a minimum width meeting a requirement, wherein the requirement is to fill the spacing region with at least one dummy pattern. A layout apparatus employing the layout method for the integrated circuit can quickly and accurately position a poorly-placed element region in the layout, improve the layout efficiency and layout precision of the integrated circuit, and lay a foundation for improving photolithography quality.