The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Jan. 26, 2024
Applicant:

SK Keyfoundry Inc., Cheongju-si, KR;

Inventors:

Ji Man Kim, Cheongju-si, KR;

Hee Hwan Ji, Daejeon, KR;

Song Hwa Hong, Cheongju-si, KR;

Assignee:

SK keyfoundry Inc., Cheongju-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/8232 (2006.01); H01L 21/8234 (2006.01); H01L 27/098 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8232 (2013.01); H01L 21/823418 (2013.01); H01L 21/823493 (2013.01); H01L 27/098 (2013.01); H01L 27/088 (2013.01);
Abstract

A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.


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