The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhichao Zhang, Chandler, AZ (US);

Kemal Aygün, Tempe, AZ (US);

Suresh V. Pothukuchi, Chandler, AZ (US);

Xiaoqian Li, Chandler, AZ (US);

Omkar Karhade, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/00 (2013.01); G02B 6/42 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G02B 6/4268 (2013.01); G02B 6/428 (2013.01); H01L 25/50 (2013.01); H01L 23/3736 (2013.01); H01L 23/538 (2013.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.


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