The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Apr. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Fang-Yu Liang, Taipei, TW;

Kai-Chiang Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/566 (2013.01); H01L 21/76805 (2013.01); H01L 23/3142 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01);
Abstract

A semiconductor package and a manufacturing method thereof are provided. A package substrate of a device includes a functional circuit structure in a central region of the package substrate and a seal ring structure in a peripheral region of the package substrate and electrically isolated from the functional circuit structure. The seal ring structure includes a via pattern including outer discrete features arranged in an outer loop and inner discrete features arranged in an inner loop between the outer loop and the functional circuit structure. In a top view, ends of adjacent two of the inner discrete features are spaced apart from each other by a non-zero distance, and one of the outer discrete features overlaps the non-zero distance.


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