The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Dec. 15, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Biswanath Senapati, Mechanicville, NY (US);

Seiji Munetoh, Kawasaki, JP;

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Geoffrey Burr, Cupertino, CA (US);

Kohji Hosokawa, Ohtsu, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); H01L 21/76898 (2013.01); H01L 23/53209 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H10B 63/80 (2023.02);
Abstract

A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.


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